Applied Science , Memorial University of Newfoundland , St . John ’ s , NL , Canada , A 1 B 3 X 5 Gholamreza Shomalnasab , Dr . Lihong Zhang Density - Uniformity - Aware Analog Layout

www.PosterPresentations.com • Chip design quality affects the manufacturing process. • Dielectric thickness inside chip during tape-out may degrade yield. • Thickness variation is proportional to local feature density [4] (Fig. 4) • During Chemical-Mechanical Polishing (CMP) process, the thickness variation may increase due to difference in density of overlaying layer. [5]. • To improve chip manufacturing yield, foundries apply some rules. • If the layout doesn’t meet density requirements, foundries will either ask the designers to redesign it or they modify the layout. • They may insert non-functional blocks to improve pattern density. • A layout needs to be analyzed for its density distribution.